1. Field of the Invention
The present invention relates to a data processing apparatus and a data processing method. This application claims priority to Japanese Patent Application No. 2011-066057 filed in Japan on Mar. 24, 2011, and the contents of which are incorporated hereby.
2. Description of Related Art
An imaging apparatus, such as a still camera, a video camera, a medical endoscope camera, or an industrial endoscope camera, processes image data containing data of a great number of pixels (hereinafter referred to as “pixel data”) in conjunction with the increase of the number of pixels and speed of the imaging apparatus. In such an imaging apparatus, a memory for temporarily storing data is used when each processing block in the imaging apparatus processes image data obtained by photographing. Image data in each processing step is temporarily stored in the memory.
FIG. 18 is a block diagram showing a schematic configuration of a conventional imaging apparatus. For example, image data processing in a photographing operation of the imaging apparatus shown in FIG. 18 is performed in the following order.
(Step 1): First, an imaging processing unit, for example, transmits image data obtained by a CCD (Charge Coupled Device) solid-state imaging device to a memory via an output DMA (Direct Memory Access) unit to temporarily store the image data.
(Step 2): Subsequently, an image processing unit reads the image data temporarily stored in the memory via an input DMA unit. The image processing unit performs image processing for recording or display on the read image data. The image processing unit then transmits the processed image data to the memory via the output DMA unit to temporarily store the image data.
(Step 3): Subsequently, a display processing unit reads the image data subjected to image processing for display via an input DMA unit and causes a display device to display the image data.
Thus, in the imaging apparatus, the preceding processing block temporarily stores the image data in the memory. The subsequent processing block reads the image data stored in the memory and performs a next process. Thus, as respective processing blocks in the imaging apparatus perform delivery of the image data, which is a processing target, via the memory, entire processes of the imaging apparatus are sequentially performed.
In recent years, it has been preferable for an imaging apparatus such as a still camera, a video camera or the like to be able to be continuously used for a long time. Accordingly, there is a need for a technique for reducing power consumption of an electrical circuit of the imaging apparatus. One method of reducing the power consumption of the imaging apparatus includes a method of increasing a transfer speed for image data between each processing block (electrical circuit) and a memory. The increase of the transfer speed for image data, for example, may be realized by increasing a frequency of an operation clock of the imaging apparatus or shortening a transfer period of time of the image data between the processing block and the memory. This method reduces power consumption concerning transfer of the image data by increasing the transfer speed of the image data.
As a technique of shortening a transfer period of time of image data between the processing block and the memory, a packing technique as disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 is known. The packing technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 is a technique of extending a bus width of a data bus used when each pixel data in the image data is transferred to a memory and arranging (packing) a plurality of adjacent pixel data in the data bus to transfer a plurality of pixel data at a time. Using this technique, the number of data transfers required to transfer all pixel data can be further reduced over conventional data transfer in which pixel data is transferred pixel by pixel, and the period of time for data transfer of the image data can be shortened. For example, when pixel data obtained from a 16×16 Bayer arrangement CCD is transferred to a memory as shown in FIG. 19, in the packing technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, pixel data for 4 pixels is one transfer unit, thus reducing a transfer period of the image data to 1/4. Accordingly, it is possible to reduce power consumption of an electrical circuit in the imaging apparatus, relative to a case in which pixel data is transferred to the memory pixel by pixel.
As a technique of further shortening the transfer period of image data, a packing method using burst transfer of DMA is considered. This is a method in which one burst, which is a unit for accessing a memory at a prescribed certain number of cycles, is considered a unit for packing a pixel data. FIGS. 20A and 20B show an example of packing of pixel data. FIG. 20A illustrates an example in which the pixel data shown in FIG. 19 is packed by the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358. FIG. 20B shows an example in which the pixel data shown in FIG. 19 is packed in a burst unit. An example in which a bus width (hereinafter referred to as “memory bus width”) of a data bus used when the pixel data is transferred to the memory (hereinafter referred to as “memory bus”) is 32 bit, and memory access for one cycle in burst transfer (hereinafter referred to as “one transfer”) is performed four times, that is, one burst transfer is performed through four transfers, is shown in FIGS. 20A and 20B. An example in which resolution of pixel data of one pixel, that is, a bit number of the pixel data, is 9, 10, 12, and 14 from top to bottom, is shown in FIGS. 20A and 20B.
As can be seen from FIGS. 20A and 20B, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 shown in FIG. 20A, pixel data for two pixels per one transfer can be arranged on a memory bus, and pixel data for 8 pixels per one burst can be transferred to the memory. On the other hand, in the packing method in the burst unit shown in FIG. 20B, pixel data for 14, 12, 10, and 9 pixels can be transferred to the memory. In the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, since pixel data is arranged (packed) in the memory bus width, that is, in a unit of one transfer, a sum of bit numbers of a plurality of arranged pixel data must not exceed the memory bus width. Accordingly, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, there are many bit to which pixel data cannot be allocated within the memory bus width (hereinafter referred to as “unused bit”). On the other hand, in the packing method in the burst unit, since pixel data is arranged (packed) in units of bursts, even when a sum of bit numbers of a plurality of arranged pixel data exceeds the memory bus width, the pixel data can be arranged (packed) in a next transfer as long as the sum does not exceed one burst, as in FIG. 20B. That is, in the packing method in the burst unit, even when the memory bus width is not an integer times the resolution of pixel data, the pixel data can be arranged (mapped) over one transfer unit, which can reduce the number of unused bit. Accordingly, in the packing method in the burst unit, much pixel data can be transferred to the memory in the same time, that is, the transfer period of time of the image data can be shortened, and the power consumption of the electrical circuit in the imaging apparatus can be further reduced than the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358.
However, in general, it is known that when data change (change (inversion) of data “0”→“1” or “1”→“0”) is less, power consumption to be lower. Accordingly, reducing the power consumption of the imaging apparatus by reducing the data change on the memory bus between each processing block (electrical circuit) and a memory in the imaging apparatus is also considered. FIGS. 21A to 21D are diagrams illustrating a relationship between the data change on the data bus (memory bus) between the processing block and the memory in the imaging apparatus and the power consumption. FIG. 21A shows an example in which a bus width of a memory bus between the imaging processing unit and the memory in the imaging apparatus shown in FIG. 18 is 32 bit. The data change on the memory bus is schematically shown in FIGS. 21B to 21D. In the example of FIGS. 21A to 21D, power consumption is lowest in the case of FIG. 21B in which there is no data change on the memory bus, and highest in the case of FIG. 21D in which there is the most data change on the memory bus.
It can be seen from the above that if there is a great amount of change in pixel data between two continuous transfers (e.g., pixel data in first and second transfers of each burst transfer shown in FIGS. 20A and 20B) in the burst transfer between each processing block and the memory in the imaging apparatus, power consumption concerning the transfer of the image data increases. That is, the power consumption due to the transfer of the image data varies in proportion to the number of the bit (bit number) on the memory bus that the same bit have changed between the two transfers.
In general, there is expected that an amount of change in data between adjacent pixels in image data is small, and bit whose values are being inverted are expected to be less than bit whose values are not being inverted when the same bit of pixel data of adjacent pixels are compared. Here, when the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 and the burst unit-based packing method, which are shown in FIGS. 20A and 20B, are compared with each other, the power consumption due to the transfer of the image data is lower in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 in which the same bit are aligned in pixel data with the same colors, as shown in FIGS. 22A and 22B. Further, FIGS. 22A and 22B show a case in which the bit number of pixel data of one pixel is 9 in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 and the burst unit-based packing method shown in FIGS. 20A and 20B.
More specifically, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 shown in FIG. 22A, least significant bit of the memory bus shown in a range A are all the same bit (least significant bit) of pixel data with the same colors. On the other hand, in the packing method in the burst unit shown in FIG. 22B, least significant bit of the memory bus shown in a range B are all different bit of pixel data having different colors. It can be seen from this that, when locations of bit of pixel data arranged on the memory bus are made different between two continuous transfers by packing the image data in a burst unit, a change amount of the same bit on the memory bus becomes great and the power consumption concerning the transfer of the image data increases.
That is, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358 shown in FIG. 22A, the power consumption concerning the transfer of the image data is low, but data transfer efficiency is low. In the packing method in the burst unit shown in FIG. 22B, the data transfer efficiency is high, but the power consumption concerning the transfer of the image data is high.
Thus, more pixel data is arranged on the memory bus when packing the pixel data in the burst units. As a result, the transfer period of time of the pixel data can be shortened and the power consumption concerning transfer of the image data can be reduced. However, since locations of bit of the pixel data arranged on the memory bus are different between two continuous transfers, sufficient reduction of the power consumption concerning the transfer of the image data cannot be obtained.
Further, in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, for example, pixel data for three pixels can be arranged (packed) in one transfer in which the pixel data is packed, as shown in FIG. 23. However, in this case, for example, least significant bit of the memory bus shown in a range C are the same bit (least significant bit) of the pixel data, but with different colors. The pixel data having different colors is highly likely to be greatly different in value, and even in the packing method disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-312358, the power consumption concerning the transfer of the image data is not reduced depending on the pixel data arrangement in one transfer.
As a technique of reducing change in data arranged on the memory bus between two continuous transfers, a technique such as that in Japanese Unexamined Patent Application, First Publication No. 2000-148605 is disclosed. In Japanese Unexamined Patent Application, First Publication No. 2000-148605, a technique for a method of reducing a change amount of transferred data a method of determining the change amount, and a method of using the change amount when image data changing in time series is transmitted to a display device such as a liquid crystal panel is disclosed. EMI (Electro Magnetic Interference) radiation and power consumption reduce by reducing a change amount of image data transferred to the display device.
In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-148605, a data sending side compares input n-bit data with n-bit data input at an immediately previous timing for each bit to majority-decide the number of bit whose values have changed. In the majority decision, the input data is decided to be inverted if the number of bit of the input data whose values have changed exceeds half, and the input data is not to be inverted if the number of bit whose values have changed is equal to or less than half. The sending side outputs data obtained by inverting the input data or data that is the input data as it is to the receiving side according to the majority decision result.
In this case, a signal indicating whether or not the data has been inverted is also output to the receiving side. The data receiving side inverts and then receives the received data or receives the data as it is according to the signal indicating whether or not the data has been inverted, and restores the data input to the sending side.
Here, a concrete example of a method of reducing a data change amount of data to be transferred (transfer data), which is disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-148605, will be described. FIG. 24 is a block diagram showing a schematic configuration of a conventional data processing apparatus disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-148605. A data transmitting side (a sending side) of the conventional data processing apparatus disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-148605 transfers input data in time series to a data reception side (a receiving side) in the following flows.
(Flow 1): If data to be transferred is input, first, an EXOR (exclusive OR) 1 circuit compares currently input 36 bit data (hereinafter referred to as “data D1”) with 36 bit data input at an immediately previous timing (hereinafter referred to as “data D0”) for each bit.
(Flow 2): Subsequently, a majority circuit detects the number of bit of the data D1 whose values have changed (hereinafter referred to as “bit change number”) from the comparison result of each bit input from the EXOR1 circuit. The majority circuit determines whether the detected bit change number occupies a majority of a data width (bit number: n bit) of the data D1. The majority circuit outputs a control signal (hereinafter referred to as “inversion bit”) indicating whether the data D1 is to be inverted and then output or to be output in a non-inverted state according to the determined majority result. The majority circuit of the conventional data processing apparatus shown in FIG. 24 determines that all bit of the data D1 are to be inverted and outputs value “1” as the inversion bit if the bit change number occupies a majority of the data bit number (>n/2). Also, the majority circuit determines that all the bit of the data D1 are not to be inverted and outputs value “0” as the inversion bit if the bit change number is equal to or less than half of the data bit number (≦n/2). Here, the inversion refers to a change of a value of each bit of data from “1” to “0” or from “0” to “1”.
(Flow 3): Subsequently, an EXOR2 circuit compares the value of the inversion bit corresponding to the data D1, which is output from the majority circuit in flow 2, with the value of the inversion bit corresponding to the data D0. The comparison result of the EXOR2 circuit is a control signal (hereinafter referred to as “inversion bit”) indicating whether all bit of data of the data D1 are finally to be inverted and then output or to be output in a non-inverted state. That is, the conventional data processing apparatus shown in FIG. 24 determines whether to perform an inversion process to invert and then output all the bit of the data D1 or a non-inversion process to output all the bit of the data D1 in a non-inverted state based on whether or not the data D0 input at an immediately previous timing has been inversion-processed and then output. More specifically, in the conventional data processing apparatus, when the value of the inversion bit corresponding to the data D0 is “0” (non-inversion), the inversion bit corresponding to the data D1 input from the majority circuit finally becomes the inversion bit corresponding to the data of the data D1. On the other hand, in the conventional data processing apparatus, if the value of the inversion bit corresponding to the data D0 is “1” (inversion), a signal reverse to the inversion bit corresponding to the data D1 input from the majority circuit finally becomes the inversion bit corresponding to the data of the data D1. This is intended so that, for example, when the data D0 is inversion-processed and output and then the data D1 is inversion-processed and output even at a next timing, the data D1 is prevented from being data inverted from the inverted and output data D0, that is, non-inverted data resulting from twice inversions since the data D0 output at an immediately previous timing is already inverted data.
(Flow 4): At a next timing, an EXOR3 circuit performs an inversion process or a non-inversion-process on all the bit of the data D1 according to the inversion bit to output (transfer) data D1. At the same timing, the inversion bit is output (transferred) together. Through such a flow, in the conventional data processing apparatus shown in FIG. 24, when the number of bit of data input in time series whose values have changed exceeds half, the input data is subjected to the inversion process such that the number of bit whose values have changed is reduced to half or less for transfer. Accordingly, a change amount of respective bit when the input data is transferred can be reduced and power consumption concerning the data transfer can be reduced.
At the data reception side, an EXOR4 circuit performs an inversion process or a non-inversion process on all the bit of the data D1 received from the data transmission side according to the inversion bit received therewith. Accordingly, the original data D1 input to the data reception side can be restored.
An example of concrete data values showing that a change amount of output data becomes small in the conventional data processing apparatus will be described herein. FIGS. 25A and 25B are diagrams showing an example in which the data change amount is reduced in the conventional data processing apparatus disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-148605. FIG. 25A shows input data input to the conventional data processing apparatus and a bit change number, and FIG. 25B shows output data and an inversion bit output from the conventional data processing apparatus, and a bit change number. In the conventional data processing apparatus, the input data as shown in FIG. 25A is sequentially input in time series from a top column to a bottom column. Each time the input data is input, the conventional data processing apparatus detects the bit change number and performs the inversion process or the non-inversion-process on all the bit of the input data according to the detected bit change number to output the output data as shown in FIG. 25B. Hereinafter, for convenience of description, a case in which 8-bit input data is input to the conventional data processing apparatus and 8-bit output data is output will be described.
As can be seen from FIG. 25A, if the values of the respective bit of the input data are sequentially compared each time the input data is input, that is, in a column of the input data shown in FIG. 25A, if the value of each bit is compared with the value of the input data in an upper column, for example, there is the input data in which the bit change number occupies the majority, like the input data in columns “A” of FIG. 25A.
Further, a sum of the bit change numbers in all the input data shown in FIG. 25A is 38-bit.
In the conventional data processing apparatus, the output data obtained by subjecting the input data to the inversion process or the non-inversion process in flows such as flows 1 to 4 described above is output, the bit change number is equal to or less than half, as in columns “A” of FIG. 25B. Accordingly, the sum of the bit change numbers in all the output data is 30-bit and the data change amount is reduced by 8 bit. Thus, as the values of the respective bit of the input data are sequentially compared and the input data in which the bit change number is great is inversion-processed and then output, a total data change amount in data transfer can be reduced over a case in which data is transferred without being subjected to the inversion process.
FIGS. 26A and 26B are diagrams showing an example of a data change amount in image data. For example, as shown in FIG. 26A, when 8-bit image data is sequentially input as a natural image data, the case in which an image data in the natural image data changes from a value of top column to a value of bottom column is considered. In the following explanation, as shown in FIG. 26A, a data correlation of 4 upper bit of image data is high and a data correlation of lower 4 bit of image data is low.
In a conventional data processing apparatus disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-148605, a data change amount is detected based on bit of data of all 8-bit in frame A shown in FIG. 26A. An example shown in FIGS. 26A and 26B, bit change amount is detected as 3 bit.
In the conventional data processing apparatus disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-148605, a majority decision id performed based on a detected bit change amount.